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DM74ALS165 8-Bit Parallel In/Serial Out Shift Register
January 1986 Revised February 2000
DM74ALS165 8-Bit Parallel In/Serial Out Shift Register
General Description
The DM74ALS165 is an 8-bit serial register that, when clocked, shifts the data toward serial output, QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD input. The DM74ALS165 also features a clock inhibit function and a complemented serial output, QH. Clocking is accomplished by a LOW-to-HIGH transition of the CLK input while SH/LD is held HIGH and CLK INH is held LOW. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a LOW CLK input and a LOW-to-HIGH transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is HIGH. Parallel loading is inhibited when SH/LD is held HIGH. The parallel inputs to the register are enabled while SH/LD is LOW independently of the levels of CLK, CLK INH, or SER inputs.
Features
s Complementary outputs s Direct overriding load (data) inputs s Gated clock inputs s Parallel-to-serial data conversion
Ordering Code:
Order Number DM74ALS165M DM74ALS165N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Function Table
Inputs Shift/ Clock Clock Serial Parallel Load Inhibit L H H H H H H X L L L H X L L L X X X H L H L X A...H a...h X X X X X X Internal Outputs QA a QA0 H L H L QA0 QB b QB0 QAn QAn QAn QAn QB0 Output QH h QH0 QGn QGn QGn QGn QH0
H = HIGH Level (steady-state), L = LOW Level (steady-state) X = Don't Care (any input, including transitions) = Transition from LOW-to-HIGH level a...h = The level of steady-state input at inputs A through H, respectively QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established QAn, QGn = The level of QA or QG, respectively, before the most recent transition of the clock
(c) 2000 Fairchild Semiconductor Corporation
DS006712
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DM74ALS165
Logic Diagram
Timing Diagram
Typical Shift, Load, and Inhibit Sequences
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DM74ALS165
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Typical JA N Package M Package 74.0C/W 104.0C/W 7V 7V 0C to +70C -65C to +150C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLOCK tW Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency Pulse Duration CLK HIGH CLK LOW Load tSU tSU tH TA Setup Time Setup Time Hold Time Operating Free Air Temperature SH/LD Data CLK INH before CLK Serial before CLK 45 11 11 12 10 10 11 10 4 0 70 ns ns ns C ns Parameter Min 4.5 2 0.8 -0.4 8 Typ 5 Max 5.5 Units V V V mA mA MHz
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VIK VOH VOL II IIH IIL IO (Note 3) ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current at Max Input Voltage VCC = 5.5V, VI = 7V HIGH Level Input Current LOW Level Input Current Output Drive Current Supply Current VCC = 5.5V, VI = 2.7V VCC = 5.5V, VI = 0.4V VCC = 5.5V, VO = 2.25V VCC = 5.5V (Note 4) -30 16 Conditions VCC = 4.5V, II = -18 mA IOH = -0.4 mA VCC = 4.5V to 5.5V VCC = 4.5V IOL = 4 mA IOL = 8 mA VCC - 2 0.25 0.35 0.4 0.5 0.1 20 -0.1 -112 24 Min Typ (Note 2) Max -1.5 Units V V V mA A mA mA mA
Note 2: All typical values are at VCC = 5V, TA = 25C. Note 3: The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. Note 4: With the outputs open, CLK INH and CLK at 4.5V, and a clock pulse applied to the SH/LD input, ICC is measured first with the parallel inputs at 4.5V, then with the parallel inputs grounded.
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DM74ALS165
Switching Characteristics
over recommended free air temperature range. All typical values are measured at VCC = 5V, TA = 25C. Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Maximum Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Load QH or QH QH or QH QH or QH QH or QH QH QH QH QH Input Output Conditions VCC = 4.5V to 5.5V, CL = 50 pF, RL = 500 TA = Min to Max Min 45 4 Typ 60 13 20 ns 4 14 22 Max Units MHz
Load
CLK
3
7
13 ns
CLK H H
3 3 3
9 7 9
14 13 ns 16
H
2
8
15 ns
H
3
9
16
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DM74ALS165
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
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DM74ALS165 8-Bit Parallel In/Serial Out Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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